Tensilica Vision C5 DSP

Cadence (Tensilica) Vision C5 DSP IP core for neural networks architecture overview here. press release.

4-way VLIW 128-way SIMD processor. Supports bit width of 8 and 16. This is a DSP – not a hard-coded convolution accelerator.

  • 1 TeraMAC (TMAC)/sec (apparently 8-bit), <1 mm.sq. silicon area
  • “1024 8-bit MACs or 512 16-bit MACs”
  •  “128-way, 8-bit SIMD or 64-way, 16-bit SIMD”
  • 4 cores (4-way)
  • 4x throughput of Vision P6 DSP
  • Separate data banks, instruction RAMs. Instructions are cached.

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